Modern semiconductor chips, especially processor chips comprise a plurality of electronic elements and are therefore faced with very high power consumption. Therefore it is necessary to reduce the power consumption of such semiconductor chips. A method according to the state of the art uses separate power domains to subdivide the semiconductor chip. Each power domain has a separate power supply or some way to turn off its local power. As many transistors as possible may be switched off, or their voltages may by reduced.
For testing purposes of the chip all or part of the storage elements of each power domain are interconnected to a so-called scan chain. Each scannable storage element comprises a scan input and a scan output. The scan chain includes a plurality of connections between the scan output of one storage element and the scan input of the next storage element. The scan chain is a serial line moving a data bit into each storage element according to a predetermined pattern scheme. In test mode said scan chain has the functionality of a shift register.
If such a power domain is switched off or the circuit's voltage is reduced, then a scanning process is not possible on said power domain, since the logic inside the power domain is not functional. Hence the whole scan chain is interrupted. It is not possible anymore to scan the storage elements on the active power domains of the semiconductor chip.
In the state of the art a solution of this problem is to activate all those power domains with the storage elements to be scanned. However, this results in a huge power consumption peek that may not be supported currently by the system. The activation of all power domains to be able to scan would further take a relatively long time. This method is already used during bring-up, where few cooling constraints are present and no power reduction techniques need to be applied, that impacts the functionality of the scan chain.
A further solution in the state of the art is to subdivide each scan chain into independent scan chain portions at each power domain. This requires additional numbers of wires running from and to the scan engine. The complexity of the scan structure and its verification is increased. If there is only one storage element in the wrong domain, then the scan chain is interrupted. In the worst case the configuration chain for the power controller is interrupted, preventing the ability to activate the power domain with the badly wired storage element. This would require a change to the chip masks and a remanufacturing of the semiconductor chip. Further the user has to activate the power domain to be scanned before and adding again more overhead in the software.
FIG. 6 illustrates a schematic diagram of an example of a semiconductor chip according to the prior art. Said semiconductor chip is subdivided into a plurality of power domains 10, 12 and 14. The power domains 10, 12 and 14 may be separately activated and deactivated by a power controller 16 via signal lines 18, 20 and 22. In FIG. 6 all power domains 10, 12 and 14 are activated. The power domains 10, 12 and 14 include a plurality of circuit units 24, 26 and 28. In FIG. 6 three circuit units 24, 26 and 28 are shown in each power domain 10, 12 and 14. Each circuit unit 24, 26 and 28 comprises a plurality of electronic elements and in particular at least one scannable storage element.
FIG. 7 illustrates a schematic diagram that of a semiconductor chip according to the prior art of FIG. 6 in a state, wherein the second power domain 12 is deactivated. Therefore the scan chains 42, 44 and 46 are interrupted in the second power domain 12, since the each of the scan chains 42, 44 and 46 crosses the deactivated power domain 32. In this second state it is not possible to make the scan test. If only one of the power domains 10, 12 and 14 is deactivated, then it is not possible to scan the storage elements.